1. Field of the Invention
The present invention relates to complementary metal-oxide-semiconductor (CMOS) fabrication methods and devices and, more particularly, to the fabrication and structure of vertical trench CMOS devices for integrated circuits.
2. Description of the Prior Art
U.S. Pat. No. 4,670,768 issued June 2, 1987 to Sunami et al, entitled COMPLEMENTARY MOS INTEGRATED CIRCUITS HAVING VERTICAL CHANNEL FETS, describes a CMOS having a vertical channel with a gate metal disposed vertically in a groove. More specifically, a semiconductor integrated circuit is described comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.
A U-MOSET with a vertical channel is shown in Japanese patent JA0003287 issued Jan. 10, 1983 to Furumura, entitled VERTICAL CYLINDRICAL MOS FIELD EFFECT TRANSISTOR, more particularly, to improve the integration of an MOS field effect transistor and to form a flat structure for forming a source region and a drain region in the end surface of vertical hollow cylindrical insulating layer buried with a gate electrode, an insulating layer is formed in a vertical hollow cylindrical shape sequentially with bottom regions to become drain or source formed in contact with or above the outside surface.
In U.S. Pat. No. 4,319,932 issued Mar. 16, 1982 to Jambotkar, entitled METHOD OF MAKING HIGH PERFORMANCE BIPOLAR TRANSISTOR WITH POLYSILICON BASE CONTACTS, the step of doping a substrate from a deposited polysilicon layer is shown. Bipolar transistor devices are formed by employing polysilicon base contacts self-aligned with respect to a diffusion or ion implantation window used to form emitter, intrinsic base and raised subcollector regions. The polysilicon acts as a self-aligned impurity source to form the extrinsic base region therebelow and, after being coated with silicon dioxide on its surface and along the sidewalls of the diffusion or ion implantation window, as a mask. Directional reactive ion etching is used to form a window in the silicon dioxide while retaining it along the sidewalls. Ion implantation, for example, may be used to form, through the window, an emitter, intrinsic base and raised subcollector region. The silicon dioxide is used as an insulator to separate the emitter contact from polysilicon.
U.S. Pat. No. 4,523,369 issued June 18, 1985 to Nagakubo et al, entitled METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, shows a method including the step of forming a sidewall layer which is used for defining a trench. The method for manufacturing more particularly includes the steps of: forming a first mask member which has an opening to expose a desired portion of one major surface of a semiconductor substrate, doping an impurity which has the same conductivity type as that of the semiconductor substrate through the opening of the first mask member to form an impurity region of a high concentration in the surface layer of the semiconductor substrate; forming second mask member on the side surface of the opening of the first mask member while the first mask member is left as it is; forming a groove by selectively etching the semiconductor substrate using the first and second mask members, and at the same time leaving an impurity region of the high concentration at least on the side surface of the groove; and burying an insulating isolation material in the groove.
Other patents related to the field of FETs, CMOS, V-grooves and trenches include the following:
U.S. Pat. No. 4,509,991 issued Apr. 9, 1985 to Taur, entitled SINGLE MASK PROCESS FOR FABRICATING CMOS STRUCTURE; PA1 U.S. Pat. No. 4,517,731 issued May 21, 1985 to Khan et al, entitled DOUBLE POLYSILICON PROCESS FOR FABRICATING CMOS INTEGRATED CIRCUITS; PA1 U.S. Pat. No. 4,455,740 issued June 26, 1984 to Iwai, entitled METHOD OF MANUFACTURING A SELF-ALIGNED U-MOS SEMICONDUCTOR DEVICE; PA1 U.S. Pat. No. 4,541,001 issued Sept. 10, 1985 to Schutten et al, entitled BIDIRECTIONAL POWER FET WITH SUBSTRATE-REFERENCED SHIELD; PA1 U.S. Pat. No. 4,454,647 issued June 19, 1984 to Joy et al, entitled ISOLATION FOR HIGH DENSITY INTEGRATED CIRCUITS; PA1 U.S. Pat. No. 4,131,907 issued Dec. 26, 1978 to Ouyang, entitled SHORT-CHANNEL V-GROOVE COMPLEMENTARY MOS DEVICE.
U.S. Pat. No. 3,893,155 issued July 1, 1975 to Ogiue, entitled COMPLEMENTARY MIS INTEGRATED CIRCUIT DEVICE ON INSULATING SUBSTRATE;